The present invention relates generally to bandgap reference voltage circuits, and more particularly to improvements therein which would improve accuracy by reducing sensitivity to random mismatching of internal components and sensitivity to temperature, long-term drift of input offset voltages, and mechanical stresses in integrated circuit chips in which the bandgap reference voltage circuits are formed.
FIG. 1A shows a conventional bandgap voltage reference circuit 1 which includes an amplifier 4 having its (+) input connected to the junction 2 between one terminal of a resistor R1 and the base and collector of a diode-connected NPN transistor Q5. Similarly, the (−) input of amplifier 4 is connected to the junction 3 between one terminal of a resistor R2 and one terminal of a resistor R3. The other terminal of resistor R3 is connected to the base and collector of a diode-connected NPN transistor Q4. The upper terminals of resistors R1 and R2 are connected by conductor 5 to the output of amplifier 4, on which a reference voltage VREF is generated. The emitters of transistors Q4 and Q5 are connected to supply voltage VSS.
Conventional band gap reference circuits such as the one in Prior Art FIG. 1A generally have a serious problem of poor long term stability and wide chip-to-chip variation in the thermal drift of the generated reference voltage VREF. Conventional band gap reference circuits typically provide trimming capability to adjust a “magic value” which is the actual band gap voltage VBG of the silicon and typically is 1.2 volts. The generated reference voltage VREF is a sum of a VBE voltage (base-to-emitter voltage) which is a CTAT voltage that is inversely proportional to absolute temperature and a ΔVBE voltage which is a PTAT voltage (Proportional to Absolute Temperature) voltage that is directly proportional to absolute temperature. The ΔVBE voltage is generated as a result of (1) forcing identical currents to flow through scaled diode-connected bipolar transistors Q4 and Q5 which, for example, have emitter areas that are scaled in the ratio of 1 to 8, (2) forcing scaled currents through identical diode-connected bipolar transistors Q4 and Q5, or (3) a combination of both of foregoing methods (1) and (2).
For most practical cases, the ΔVBE voltage is smaller than the VBE voltage and needs to be amplified by a significant factor, typically about 6 to 20, depending on the way the two transistors and the emitter currents flowing through them are scaled. The amplification and addition of the two components VBE and ΔVBE are performed by additional circuitry such as amplifier 4 and resistors R1, R2, and R3 in FIG. 1A. The output voltage produced by amplifier 4 is VREF=VBE+N×ΔVBE, where N is a gain factor. It can be recognized from the foregoing equation that band gap reference circuit 1 in Prior Art FIG. 1A has high sensitivity to random causes such as component mismatches, various semiconductor chip material defects, temperature variations, long term input offset voltage drift, mechanical stress in the integrated circuit chip, and package stress imparted to the chip.
The high sensitivity to random mismatches occur because bandgap reference circuit 1 in Prior Art FIG. 1A uses scaled components to generate the necessary ΔVBE voltage. For example, the emitter area of transistor Q5 may be 8 times smaller than the emitter area of transistor Q4 and is what mainly determines the overall sensitivity of band gap reference circuit 1 to the above mentioned random causes. If scaled current sources including resistor R1 and resistors R2 along with R3 are utilized, the one with the lower resistance (i.e., resistor R3) substantially affects the sensitivity of VREF to the random mismatches. The variation of the dominant sources of random error affects the value of the ΔVBE voltage, which is multiplied by the above mentioned gain factor N to determine the generated reference voltage VREF. The input offset voltage and drift of amplifier 4 are amplified by its gain and therefore increase the chip-to-chip variability of the generated reference voltage VREF. The same small-area component (i.e., Q5) that dominates the sensitivity of VREF to random mismatch also is sensitive to back grind stress of the silicon chip on which the circuitry is formed and to package level stress.
Bandgap reference circuit 1 is difficult to optimize, because although reduction of the ratio of the emitter areas and emitter current densities of transistors Q4 and Q5 leads to better component matching, such reduction also reduces the value of the ΔVBE voltage, so higher amplifier gain is required. That unfortunately results in higher variation of the generated reference voltage VREF due to the “gained-up” input offset voltage and associated drift of the offset voltage of amplifier 4, and hence results in higher noise in the generated reference voltage VREF.
As indicated above, the emitter areas of large transistor Q4 and small transistor Q5 are scaled in order to generate the PTAT voltage across resistor R3, and only the smaller emitter area of transistor Q5 is mainly determinative of the random chip-to-chip variation VREF. For example, if the ratio of the emitter areas of transistors Q4 and Q5 is 24, then transistor Q5 can be a single “unit transistor” with one “minimum unit” emitter area, and larger transistor Q4 can be composed of 24 parallel-connected unit transistors having a total of 24 unit emitter areas. That means the random chip-to-chip variation in the emitter area of only the single small transistor Q5, rather than the entire area of the array of all of the unit transistors, directly results in a corresponding random chip-to-chip variation in the output bandgap voltages produced by the band gap voltage reference circuit of FIG. 1A. (If there are multiple elements or devices in an array, the total variation of array parameters with respect to random variations of parameters of the individual elements or devices is significantly lower than the parameter variation of any single element or device of the array. For example, in Prior Art FIG. 1A, the emitter area of the small-area unit transistor Q5 varies much more than that of the large-area transistor Q4 because the transistor Q4 has the average characteristics of a large number of small-area unit transistors. The problem arises that, in order to generate the ΔVBE voltage, it is necessary to use both a large-area transistor and a small-area transistor. But the random variation depends not much on the large-area transistor Q4 but mainly on the single small-area unit transistor Q5, and consequently there is no way to optimally reduce the effect of the single small-area unit transistor.) Operational amplifier 4 typically has a gain of approximately 10, and this causes its input offset voltage and drift of the input offset voltage to be multiplied by that gain. The gained-up input offset voltage is subject to the random chip-to-chip variation and consequently makes a significant contribution to the random variation of the generated reference voltage VREF.
Prior Art FIG. 1B is a copy of FIG. 6 of commonly-assigned U.S. Pat. No. 7,511,648 entitled “Integrating SAR ADC and Method with Low Integrator Swing and Low Complexity”, issued Mar. 31, 2009 to Trifonov et al., and incorporated herein by reference. Prior Art FIG. 1B shows and describes the structure and operation of known band gap voltage reference circuitry which includes basic band gap reference circuitry similar to that in Prior Art FIG. 1A along with an integrator 30 and a comparator 22. The integrator 30 works together with input sampling capacitors C0 and C1 and associated sampling switches SW1 and SW2. Comparator 22 controls the direction of integration.
Prior Art FIG. 1C is a copy of FIG. 3a of commonly assigned U.S. Pat. No. 7,504,977 entitled “Hybrid Delta-Sigma/SAR Analog to Digital Converter and Methods for Using Such”, issued Mar. 17, 2009 to Doorenbos et al. and incorporated herein by reference. Prior Art FIG. 1C shows known switching circuitry similar to that in Prior Art FIG. 1B, including operational amplifier 412 and comparator 414. Comparator 414 controls the direction of integration of the sampled band gap reference voltage values applied to the inputs of operational amplifier 412.
Various dynamic element matching techniques are known wherein various matched circuit elements such as current sources, resistors, or capacitors in integrated circuit chips are “rotated” or successively connected into a particular circuit in order to, in effect, provide average values of various parameters of the matched circuit elements. This minimizes the sensitivity of the circuit including such matched circuit elements to random variations in their various parameters. Specifically, dynamic element matching of multiple current sources connected to each of a pair of identical diode-connected transistors has been utilized in temperature-sensing integrated circuits to reduce the sensitivity of the difference voltage ΔVBBE between their base-emitter voltages to reduce random mismatches in their collector currents. Also, dynamic element matching of sampling capacitors has been used in the above mentioned temperature-sensing circuits to reduce the sensitivity of the temperature-sensing circuit to random mismatches in the sampling capacitors.
However, even though dynamic element matching techniques are widely used in many applications, such techniques nevertheless are unsuitable in many applications because dynamic element matching typically involves highly complex, very costly circuitry, slow circuit operation, and generation of ripple signals or tones which are very difficult and costly to deal with.
Various “curvature correction” circuits and techniques for band gap voltage reference circuits are known.
Thus, there is an unmet need for a band gap reference voltage circuit and method that substantially reduces random chip-to-chip variation in a band gap reference voltage generated thereby.
There also is an unmet need for a band gap reference voltage circuit and method that substantially reduces random chip-to-chip variation in a band gap reference voltage generated thereby without substantially increasing the size and/or power consumption of the circuit.
There also is an unmet need for a band gap reference voltage circuit and method that substantially reduces chip-to-chip variation in a band gap reference voltage generated thereby caused by random variations in the offset voltage and/or drift of an amplifier.
There also is an unmet need for a band gap reference voltage circuit and method that substantially reduces chip-to-chip variation in a band gap reference voltage generated thereby caused by random variations in the physical size of a single unit bipolar transistor utilized to generate a PTAT (proportional to absolute temperature) voltage utilized in generating the band gap reference voltage.
There also is an unmet need for a band gap reference voltage circuit and method wherein chip-to-chip variation in a band gap reference voltage generated thereby is dependent on the total amount of chip area required by an array of bipolar transistors or unit bipolar transistors, rather than on the size of a single unit bipolar transistor, utilized to generate a PTAT voltage on which the band gap reference voltage is based.
There also is an unmet need for a band gap reference voltage circuit which has low sensitivity to back-grind package stress and low random temperature drift.
There also is an unmet need for a band gap reference voltage circuit that is more easily optimized than those of the prior art.